1. Field of the Invention
The invention relates in general to a method for testing a memory, and more particularly to a method for testing a memory at a high speed.
2. Description of the Related Art
Non-volatile memories have been used in various applications. Data may be read from or written into the non-volatile memory, and the data stored in the non-volatile memory can be kept without power. So, the non-volatile memory may be adapted to various data storage applications.
The memory usually includes multiple chips each including multiple memory cells arranged in an array. Each memory cell is enabled by a corresponding word line. FIG. 1 (Prior Art) shows a threshold voltage distribution of a memory. The difference between a high bound HB of a low-threshold voltage distribution 102 and a low bound LB of a high-threshold voltage distribution 104 is a memory operation window S1, in which the memory actually operates.
If the memory is a pre-programmed memory, the predetermined data has to be programmed in the memory before the memory is shipped to a customer. At this time, if the operation window of the memory is not sufficient, the memory may have an error when the memory cell is processed (e.g., programmed or read). Thus, a margin threshold voltage test (margin VT test) is usually performed on the memory after being manufactured so that the chip with the insufficient operation window is found and then shielded.
FIG. 2 (Prior Art) is a flow chart showing a conventional method for testing a memory. First, in step 210, page data is read from the memory and stored to a register of the memory. After the page data is stored to the register, the tester reads the page data out from the register of the memory, as shown in step 220.
Then, in step 230, the page data is compared with expected data, corresponding to the page data, in the tester. Step 230 is performed to substantially verify the correctness of the page data. If the page data is the same as the expected data, it is judged that the memory has the enough operation window in step 240. At this time, it informs the tester that the memory has passed the test. If the page data is different from the expected data, it is judged that the memory does not have the enough operation window in step 250. At this time, it informs the tester that the test fails, and the memory is shielded.
In the method for testing the memory, the page data has to be read out from the memory, and then the correctness of the page data is verified in the tester in order to judge whether the enough operation window is possessed. The time for reading the page data out from the memory becomes longer with the gradually increased memory density. In addition, a lot of time has to be spent to compare the page data with the expected data in the tester.
Illustration will be made by taking the memory including 2 G bits of multi-level cells as an example, in which the size of the page data is 512 bytes, the output data clock is 50 ns/byte and the time for internally reading the page data (latency) is 30 μs. In the conventional method for testing the memory, the testing time is equal to (30 μs+(50 ns×512))×2×(2048 Mbit/512 byte)=58.3 seconds. Consequently, the long testing time increases the testing cost for the memory.